A new method of hardware firewall implementation on SOC

A firewall´s complexity and processing time is known to increase with the size of its rule set. Empirical studies show that as the rule set grows larger, power consumption and delay time for processing IP Packets particularly on Hardware firewalls increases extremely, and, therefore the performance of the firewall decreases proportionally. This paper present a new FPGA (field programmable gate arrays) based firewall with high performance, high processing speed, low power consumption, and low space utilization in contrast with early submitted paper in some of credible international conferences. First of all, we use Embedded Memories of FPGA instead of external memories, to increase the processing speed and to decrease the mass of signaling and noise creation in connection between FPGA and external memories. Moreover, we have applied pipeline technique to the architecture, and so we achieved high processing speed in addition to low power consumption. Based on this model, only the security rules are updated by admin during the configuration process while other hardware part would remain unchanged. The proposed architecture is written in VHDL standard language and it is simulated and synthesized with ALTERA QUARTUS II software. Finally, for validation of proposed architecture, we implemented the synthesized code on 3 of ALTERA FPGAs families (STRATIX III, CYCLONE III, CYCLONE II), and then results have been compared with earlier results.