Title :
Low power digital circuit design
Author :
Sakurai, Takayasu
Author_Institution :
Inst. of Ind. Sci., Univ. of Tokyo, Japan
Abstract :
This paper describes approaches for achieving low power digital circuits. The approaches are classified from the standpoint of spatial granularity, temporal granularity and variable granularity. The trend is moving from coarse-grain to the finer grain to save more power but with higher engineering costs. The newer approach includes dynamic adaptive control of VDD and VTH at a block level. The paper also touches on low-power applications.
Keywords :
integrated circuit design; logic design; low-power electronics; coarse-grain design; dynamic adaptive voltage control; fine-grain design; low power digital circuit design; spatial granularity; temporal granularity; threshold voltage; variable granularity; Adaptive control; CMOS digital integrated circuits; CMOS process; Collaboration; Costs; Delay; Digital circuits; Dynamic voltage scaling; Energy consumption; Power engineering and energy;
Conference_Titel :
Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European
Print_ISBN :
0-7803-8480-6
DOI :
10.1109/ESSCIR.2004.1356606
