Title :
Assessment of the merits of CMOS technology scaling for analog circuit design
Author :
Vertregt, Maarten ; Scholtens, Peter C S
Author_Institution :
Philips Res., Eindhoven, Netherlands
Abstract :
Key device parameters such as drain current, transconductance, current factor, capacitance, etc. are linked to typical analog circuit level performance criteria, as a function of the CMOS technology node. Subsequently, speed and power implications for an analog-to-digital converter building block are estimated. Significant power efficiency improvements are predicted as a result of scaling to deep sub-micron technology nodes.
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; circuit simulation; integrated circuit design; CMOS technology scaling; analog circuit design; analog-to-digital converter building block; capacitance; circuit simulation; current factor; drain current; gate-overdrive; power efficiency; transconductance; Analog circuits; CMOS analog integrated circuits; CMOS technology; Capacitance; Circuit simulation; MOSFETs; Magneto electrical resistivity imaging technique; Semiconductor device modeling; Silicon; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European
Print_ISBN :
0-7803-8480-6
DOI :
10.1109/ESSCIR.2004.1356615
