Hard-switching in high power density voltage regulators

The causes for which fast-hard-switching operation may differ from the traditional clamped inductive switching mode are mainly attributed to the parasitic loop inductances of PCB and device package as well as the parasitic output capacitances of the semiconductor switch. These parasitic elements form the basis of the proposed model, which fundamentally represents the dynamics of hard-switched converters targeted for high-switching frequency, high-current and low-voltage applications. The model is thus useful to investigate the switching behavior of the synchronous buck converter in one of the most currently challenging applications: Voltage regulators (VR) for modern computer microprocessors. The study reveals important design aspects required for the optimization of relevant circuit and device parameters at high switching frequency.