L1/L2 dual-band CMOS GPS receiver

Author

Kim, Jongmoon ; Cho, Sanghyun ; Ko, Jinho

Author_Institution

PHYCHIPS Inc., Daejeon, South Korea

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

87

Lastpage

90

Abstract

This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. The receiver has been implemented in a 1P6M 0.18 μm CMOS technology. It consists of a low-noise pre-amplifier, I-Q mixers, VGA-merged complex BPFs, 2-bit analog-digital converters, and a whole phase-locked loop synthesizer, excluding loop filter. The measured results show 95-dB maximum gain, 8.5-dB noise figure and -31-dBm IIP3 while consuming 10.6 mA from a 1.8 V supply voltage.

Keywords

CMOS integrated circuits; Global Positioning System; UHF amplifiers; UHF filters; UHF mixers; analogue-digital conversion; band-pass filters; frequency synthesizers; phase locked loops; preamplifiers; radio receivers; 0.18 micron; 1.8 V; 10.6 mA; 1227.6 MHz; 1575.42 MHz; 8.5 dB; 95 dB; CMOS GPS receiver; I-Q mixers; L1/L2 dual-band GPS receiver; VGA-merged complex BPF; analog-digital converters; global positioning system; low-noise pre-amplifier; phase-locked loop synthesizer; Analog-digital conversion; CMOS technology; Dual band; Filters; Gain measurement; Global Positioning System; Noise figure; Noise measurement; Phase locked loops; Synthesizers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Print_ISBN

0-7803-8480-6

Type

conf

DOI

10.1109/ESSCIR.2004.1356624

Filename

1356624