A study of defect propagation/growth for VLSI manufacturing yield impact prediction

The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the defect location, size, material and the underlying IC topography. A rigorous topography simulator, METROPOLE has been developed to allow the prediction and correlation of the critical physical parameters (material, size and location) of contamination in the manufacturing process to device defects. The results for a large number of defect samples simulated using the above approach were compared with data gathered from the AMD-Sunnyvale fabline. A good match was obtained indicating the accuracy of this method which provided a framework for developing contamination to defect propagation/growth macromodels. We have demonstrated that the understanding of the defect transformation can be applied to early yield impact prediction