A 35-GHz frequency synthesizer using frequency doubling and phase rotating technology

Author

Ching-Yuan Yang ; Chih-Hsiang Chang ; Jun-Hong Weng

Author_Institution

Dept. of Electr. Eng., Nat. Chung Hsing Univ., Taichung, Taiwan

fYear

2013

fDate

4-6 Sept. 2013

Firstpage

266

Lastpage

270

Abstract

The paper addresses the design and realization of a high-frequency and wide range frequency synthesizer based on a PLL together with a varactorless LC-type VCO and a push-push frequency doubler. In addition, a high-speed programmable divider using multi-phase selection is employed for channel switching. The proposed circuits were fabricated in a standard 90-nm CMOS process with a chip area of 0.8×1.1 mm². The PLL dissipates 60 mW at a 1.2-V supply. The measured phase noise of the doubler at 35.28-GHz frequency is -90.42 dBc/Hz at a 1-MHz offset.

Keywords

CMOS integrated circuits; LC circuits; frequency dividers; frequency multipliers; frequency synthesizers; phase locked loops; saturable core reactors; voltage-controlled oscillators; CMOS process; PLL; VCO; frequency 35 GHz; frequency doubling; frequency synthesizer; high-speed programmable divider; multi-phase selection; phase rotating technology; phase-locked loop; power 60 mW; push-push frequency doubler; size 90 nm; tunable transductor; tunable transformer-based inductor; voltage 1.2 V; voltage controlled oscillator; wireless transceivers; CMOS integrated circuits; Frequency conversion; Frequency synthesizers; Phase locked loops; Switches; Voltage-controlled oscillators; frequency doubler; frequency synthesizer; high-speed divider; phase-locked loop;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Information Technologies (ISCIT), 2013 13th International Symposium on

Conference_Location

Surat Thani

Print_ISBN

978-1-4673-5578-0

Type

conf

DOI

10.1109/ISCIT.2013.6645862

Filename

6645862