Impact of Process Induced Stresses and Chip-Packaging Interaction on Reliability of Air-gap Interconnects

The mechanical stability of air-gap interconnect structures during thermal processing and under chip packaging interaction (CPI) were investigated using 3D multilevel finite element analysis (FEA) models. Low k cap delamination from the Cu barrier during thermal processing, channel cracking of the bridging cap and dielectric overlayers, and interface delamination under packaging were identified as the main concerns of mechanical stability and reliability for air-gap implementation. Simulation results revealed that the delamination driving force depends very much on the gap width to cap thickness ratio, the channel cracking issue in the dielectric overlayers can be managed in the presence of constraints from adjacent Cu wires, and the introduction of air-gaps significantly increases the interfacial delamination probability under the outermost solder bumps.