A high-speed ATM switch with multiple common memories

Author

Kang, Sang H.

Author_Institution

Dept. of EE, Univ. of Seoul, South Korea

Volume

4

fYear

2001

fDate

2001

Firstpage

2645

Abstract

We consider a common-memory (CM) type N×N ATM switch, where the CM block consists of K (K⩾N) sub-memories (SM). We propose an address assigning algorithm to avoid input/output contentions so that we can have the read/write speed of each SM as low as the interface port speed. Taking the replication-at-sending approach, we pursue memory and bandwidth efficiency for a multicast cell output. We evaluate the system in terms of cell loss ratio and average delay time. We take into account two loss factors: (1) the failure of scheduling to avoid input/output contentions; (2) overflow in the CM block

Keywords

asynchronous transfer mode; buffer storage; delays; electronic switching systems; multicast communication; scheduling; storage allocation; address assigning algorithm; address buffer; average delay time; bandwidth efficiency; cell loss ratio; common-memory ATM switch; common-memory block; high-speed ATM switch; input/output contentions; interface port speed; memory efficiency; multicast cell output; multiple common memories; read/write speed; replication-at-sending approach; Asynchronous transfer mode; Bandwidth; Computational Intelligence Society; Delay effects; Multicast algorithms; Optical wavelength conversion; Samarium; Switches; Switching systems; Unicast;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 2001. GLOBECOM '01. IEEE

Conference_Location

San Antonio, TX

Print_ISBN

0-7803-7206-9

Type

conf

DOI

10.1109/GLOCOM.2001.966254

Filename

966254