DocumentCode :
1905120
Title :
Floating Well Based Design Methodology Aimed to Improve Latchup Immunity in a Smart Power Technology
Author :
Vidal, Puig ; Bafleur, M. ; Buxo, J. ; Sarrabayrouse, G.
Author_Institution :
Laboratoire d´´Automatique et d´´Analyse des Systÿmes du CNRS, 7, Avenue du Colonel Roche - 31077 Toulouse Cédex - France; Universitat Barcelona, Diagonal 645-647 - 08028 Barcelona - Spain
fYear :
1992
fDate :
14-17 Sept. 1992
Firstpage :
161
Lastpage :
164
Abstract :
The main challenge of Smart Power Integrated Circuits lies in operating simultaneously on a same chip a power device and its control circuitry. To this purpose, static and dynamic isolation between these two active parts are required. A self-isolated CMOS/DMOS technology where the drain of the vertical DMOS is coincident with the substrate (N--epilayer) of the CMOS circuitry provides a cost effective static isolation. However, voltage transients induced during the power device switching can be capacitively coupled to the CMOS circuitry and latch-up can be initiated. Instead of introducing supplementary technological steps, a design based solution is proposed to improve dynamic isolation and then latch-up immunity [1]. Such a shielding is obtained by letting float the voltage of the P-well of the CMOS technology.
Keywords :
CMOS technology; Design methodology; Doping; Immune system; Immunity testing; Integrated circuit technology; Isolation technology; Latches; Power integrated circuits; Protection;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Device Research Conference, 1992. ESSDERC '92. 22nd European
Conference_Location :
Leuven, Belgium
Print_ISBN :
0444894780
Type :
conf
Filename :
5435192
Link To Document :
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