Floating Well Based Design Methodology Aimed to Improve Latchup Immunity in a Smart Power Technology

The main challenge of Smart Power Integrated Circuits lies in operating simultaneously on a same chip a power device and its control circuitry. To this purpose, static and dynamic isolation between these two active parts are required. A self-isolated CMOS/DMOS technology where the drain of the vertical DMOS is coincident with the substrate (N^--epilayer) of the CMOS circuitry provides a cost effective static isolation. However, voltage transients induced during the power device switching can be capacitively coupled to the CMOS circuitry and latch-up can be initiated. Instead of introducing supplementary technological steps, a design based solution is proposed to improve dynamic isolation and then latch-up immunity [1]. Such a shielding is obtained by letting float the voltage of the P-well of the CMOS technology.