Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13μm CMOS

Author

Giotta, Dario ; Pessl, Peter ; Clara, Martin ; Klatzer, Wolfgang ; Gaggl, Richard

Author_Institution

Infineon Technol. Austria AG, Villach, Austria

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

163

Lastpage

166

Abstract

This work presents a 6-bit fully-differential current steering digital-to-analog converter (DAC), oversampled and 2^nd order noiseshaped. It is implemented in a 0.13 μm standard CMOS process, using only regular threshold voltage devices. The circuit is targeted at ADSL2+ central-office (CO) applications. Clocked at 105 MHz from a low-jitter PLL, it yields a multi-tone power ratio (MTPR) higher than 75 dBc for DMT signals, with an output swing of 1.4 V peak-to-peak. It has an effective resolution of more than 14.5 ENOBs (effective number of bits), consuming only 9 mW from a single 1.5 V supply.

Keywords

CMOS integrated circuits; digital subscriber lines; digital-analogue conversion; low-power electronics; phase locked loops; signal resolution; 0.13 micron; 1.5 V; 105 MHz; 9 mW; ADSL2+ central-office equipment; CMOS; DMT signals; MTPR; current steering DAC; effective number of bits resolution; fully-differential digital-to-analog converter; low-jitter PLL; low-power DAC; multitone power ratio; noiseshaped DAC; oversampled DAC; CMOS technology; Circuit noise; Clocks; DSL; Energy consumption; Jitter; OFDM modulation; Optimized production technology; Phase locked loops; Resistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Print_ISBN

0-7803-8480-6

Type

conf

DOI

10.1109/ESSCIR.2004.1356643

Filename

1356643