Title :
Copper Line Resistance Control and Reliability Improvement by Surface Nitridation of Ti barrier Metal
Author :
Sakata, A. ; Kato, S. ; Yano, Y. ; Toyoda, H. ; Kawanoue, T. ; Hatano, M. ; Wada, J. ; Yamada, N. ; Oki, T. ; Yamaguchi, H. ; Nakamura, N. ; Higashi, K. ; Yamada, M. ; Fujimaki, T. ; Hasunuma, M.
Author_Institution :
Process & Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa 235-8522, Japan Tel: +81-45-776-5515 Fax: +81-45-776-4101 e-mail: sakata@amc.toshiba.co.jp
Abstract :
This paper proposes highly reliable, low resistance and cost effective Cu interconnect system for 45nm CMOS device and beyond. Overhang formation and Cu line resistance increase by deposition process variation are serious problems for titanium (Ti) barrier metal (BM). Overhang reduction by surface nitridation of Ti BM has been successfully demonstrated. It has been clarified that Cu resistivity increase with Ti BM is due to insufficient Cu grain growth, not reaction between Ti and Cu. Surface nitridation contributes to Cu line resistance reduction by changing grain growth behavior. Moreover, it also improves oxidation endurance of the BM caused by absorbed moisture from porous low-k ILD. It is concluded that surface nitridation of Ti BM is promising approach as Cu barrier metal for 45nm device and beyond to fabricate Cu interconnect with controlled resistance and high reliability.
Keywords :
CMOS process; Conductivity; Copper; Electrical resistance measurement; Filling; Grain boundaries; Moisture; Semiconductor device reliability; Surface resistance; Testing;
Conference_Titel :
Interconnect Technology Conference, 2008. IITC 2008. International
Conference_Location :
Burlingame, CA, USA
Print_ISBN :
978-1-4244-1911-1
Electronic_ISBN :
978-1-4244-1912-8
DOI :
10.1109/IITC.2008.4546956