Robust BEOL Process Integration with Ultra Low-k (k=2.0) Dielectric and Self-Formed MnOx Barrier Technology for 32 nm-node and beyond

Author

Watanabe, T. ; Hayashi, Y. ; Tomizawa, H. ; Usui, T. ; Gawase, A. ; Shimada, M. ; Watanabe, K. ; Shibata, H.

Author_Institution

Center for Semiconductor Research & Development, Semiconductor Company, Toshiba Corporation, 8, Shinsugita, Isogo-ku, Yokohama 235-8522, Japan, Phone : +81-45-776-5647, Fax : +81-45-776-4104, E-mail : tadayoshi.watanabe@toshiba.co.jp

fYear

2008

fDate

1-4 June 2008

Firstpage

208

Lastpage

210

Abstract

Porous Low-k dielectric (k=2.0) was applied for Copper (Cu) dual-damascene interconnect with SiOC/PAr hybrid dielectric. More than 90% yield for via was obtained and approximately 5% capacitance reduction in inter-layer was obtained compared with the porous-SiOC/porous-PAr (k=2.3) hybrid dielectric process. The performance of stress-induced voiding was the same as for the conventional process. Meanwhile, with self-formed barrier process, more than 10 nm wider tolerances for misalignment was obtained compared with the conventional tantalum (Ta) barrier metal (BM) process, due to its thin barrier thickness and Cu-to-Cu connection for via and wiring.

Keywords

Absorption; Capacitance; Chemical technology; Copper alloys; Dielectrics; Fabrication; Moisture; Plasma measurements; Robustness; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2008. IITC 2008. International

Conference_Location

Burlingame, CA, USA

Print_ISBN

978-1-4244-1911-1

Electronic_ISBN

978-1-4244-1912-8

Type

conf

DOI

10.1109/IITC.2008.4546969

Filename

4546969