Title :
High volume manufacturing issues for on-die interconnects at the 45nm process node
Author_Institution :
Logic Technology Development, Intel Corporation, 5200 NE Elam Young Parkway, Hillsboro OR 97229 USA, 503-613-6588, peter.moon@intel.com
Abstract :
High volume manufacturing (HVM) for silicon devices poses numerous challenges beyond simply designing and demonstrating a useful product. This paper describes several of those challenges using examples from Intel´s HVM experience fabricating on-die interconnects for high performance logic products at the 45nm process node.
Keywords :
Chemical processes; Continuous improvement; Control systems; Electric variables measurement; Etching; Logic devices; Manufacturing processes; Process control; Production facilities; Size measurement;
Conference_Titel :
Interconnect Technology Conference, 2008. IITC 2008. International
Conference_Location :
Burlingame, CA, USA
Print_ISBN :
978-1-4244-1911-1
Electronic_ISBN :
978-1-4244-1912-8
DOI :
10.1109/IITC.2008.4546970
