Title :
A defect-situation forecasting technology to optimize future DRAM-redundancy design
Author :
Sakurai, Koichi ; Shimada, Yutaka ; Yamanishi, Kenji
Author_Institution :
Manuf. Eng. Center, Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A method of forecasting defect situations in future DRAMs manufactured in the same or similar lines is demonstrated The estimated word-line defect situation of a 0.35 micron DRAM almost agreed with the actual data. By calculation with actual 0.5 micron DRAM word-line defect data, we approximated D(x), the function of particle-existing-probability density on a particle diameter x, as a proportion of 1/x1.5. The word-line defect counts of a 0.35 micron DRAM were estimated by the product of the approximated D(x) and P k(x), the possibility function that k-lines of short or open circuits will be made
Keywords :
DRAM chips; circuit optimisation; integrated circuit design; integrated circuit reliability; integrated circuit yield; probability; redundancy; 0.35 micron; 0.5 micron; DRAM redundancy design optimisation; defect-situation forecasting technology; dynamic RAM; particle-existing-probability density; word-line defect data; Circuits; Data engineering; Degradation; Design optimization; Inspection; Manufacturing; Productivity; Random access memory; Redundancy; Technology forecasting;
Conference_Titel :
Semiconductor Manufacturing Conference Proceedings, 1997 IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-3752-2
DOI :
10.1109/ISSM.1997.664589
