Title :
A high density, low leakage, 5T SRAM for embedded caches
Author :
Carlson, Ingvar ; Andersson, Sean ; Natarajan, Sreedhar ; Alvandpour, Atila
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
Abstract :
This paper describes an embedded high density 128 Kb memory, utilizing a 5-transistor (5T) single bitline SRAM cell in a standard 0.18 μm CMOS technology. The 5T-SRAM cell allows writing of \´1\´, when the voltage at its single bitline is at Vcc. As a consequence, for a nondestructive read operation, the bitline is precharged to a voltage Vpc=600 mV\n\n\t\t
Keywords :
CMOS memory circuits; SRAM chips; cache storage; leakage currents; nondestructive readout; 0.18 micron; 1.8 V; 128 Kbit; 5T single bitline SRAM; 600 mV; CMOS; bitline precharging; embedded caches; high density SRAM; low leakage SRAM; nondestructive read operation; CMOS technology; Costs; Inverters; Manufacturing; Microprocessors; Random access memory; Robustness; Variable structure systems; Voltage; Writing;
Conference_Titel :
Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European
Print_ISBN :
0-7803-8480-6
DOI :
10.1109/ESSCIR.2004.1356656
