Low-K Interconnect Stack with Thick Metal 9 Redistribution Layer and Cu Die Bump for 45nm High Volume Manufacturing

Author

Ingerly, D. ; Agraharam, S. ; Becher, D. ; Chikarmane, V. ; Fischer, K. ; Grover, R. ; Goodner, M. ; Haight, S. ; He, J. ; Ibrahim, T. ; Joshi, S. ; Kothari, H. ; Lee, K. ; Lin, Y. ; Litteken, C. ; Liu, H. ; Mays, E. ; Moon, P. ; Mule, T. ; Nolen, S. ; Pa

Author_Institution

Logic Technology Development, 5200 NE Elam Young Pkwy, Hillsboro OR 97229 USA, doug.b.ingerly@intel.com

fYear

2008

fDate

1-4 June 2008

Firstpage

216

Lastpage

218

Abstract

Interconnect process features are described for a 45nm high performance logic technology. Through extensive use of highly manufacturable carbon doped oxide low-k dielectric layers and aggressive scaling of the SiCN etch stop film the Metal-1 to Metal-8 interconnect stack demonstrates a 10% average capacitance reduction over the 65nm process. The interconnect stack also features a very thick Metal-9 layer to provide a low resistance path for the power and I/O routing. The combined interconnect stack provides high performance and reliability and supports a Pb-free 45nm process.

Keywords

Dielectric materials; Inorganic materials; Logic; Manufacturing processes; Materials reliability; Moon; Polymers; Power distribution; Resists; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2008. IITC 2008. International

Conference_Location

Burlingame, CA, USA

Print_ISBN

978-1-4244-1911-1

Electronic_ISBN

978-1-4244-1912-8

Type

conf

DOI

10.1109/IITC.2008.4546971

Filename

4546971