Author :
Ingerly, D. ; Agraharam, S. ; Becher, D. ; Chikarmane, V. ; Fischer, K. ; Grover, R. ; Goodner, M. ; Haight, S. ; He, J. ; Ibrahim, T. ; Joshi, S. ; Kothari, H. ; Lee, K. ; Lin, Y. ; Litteken, C. ; Liu, H. ; Mays, E. ; Moon, P. ; Mule, T. ; Nolen, S. ; Pa
Author_Institution :
Logic Technology Development, 5200 NE Elam Young Pkwy, Hillsboro OR 97229 USA, doug.b.ingerly@intel.com
Abstract :
Interconnect process features are described for a 45nm high performance logic technology. Through extensive use of highly manufacturable carbon doped oxide low-k dielectric layers and aggressive scaling of the SiCN etch stop film the Metal-1 to Metal-8 interconnect stack demonstrates a 10% average capacitance reduction over the 65nm process. The interconnect stack also features a very thick Metal-9 layer to provide a low resistance path for the power and I/O routing. The combined interconnect stack provides high performance and reliability and supports a Pb-free 45nm process.
