Design and implementation of a reconfigurable SoC for high-definition video applications

This paper proposes a reconfigurable SoC architecture based on a large-scale reconfigurable processing elements (PEs) array, a high-performance RISC core and several embedded peripherals on-chip, which are coupled tightly through System buses of AMBA2.0. The large-scale PEs array is used to process video signals with different standards under appropriate contexts disposed dynamically. The embedded peripherals are with responsibility for the input of media stream data and output of the decoded multimedia data to display, while the RISC core takes charge of the initialization of the peripherals and the reconfigurable PEs, the pretreatment of media stream data, the audio decoding, the synchronization between audio and video data, and some other scheduling functions. The antitype SoC chip is implemented based on 65nm CMOS silicon techniques, and the testing results show that the reconfigurable SoC achieves the performance of real-time decoding of videos with size of 1920*1080 @ 30fps which follow the H.264, AVS and MPEG-2 standards respectively.