Title :
Sub-ns Delay Through Multi-Wall Carbon Nanotube Local Interconnects in a CMOS Integrated Circuit
Author :
Close, Gael F. ; Yasuda, Shinichi ; Paul, Bipul ; Fujita, Shinobu ; Wong, H. S Philip
Author_Institution :
Center for Integrated Systems and Department of Electrical Engineering, Stanford University, Stanford CA, USA., Email: closega@stanford.edu
Abstract :
A CMOS integrated circuit with multi-wall carbon nanotube (MWCNT) interconnects is presented, and its speed is analyzed. This chip is a platform to evaluate the merits of MWCNT interconnects in a silicon integrated circuit environment. Using this platform, we evaluate local interconnects (14¿m long) made of a single 30nm-diameter MWCNT. We experimentally extract the sub-ns delay of these wires to benchmark their future potential for the first time. Furthermore, we compare our experimental results with an existing MWCNT interconnect model, and discuss the origin of discrepancies.
Keywords :
Assembly; CMOS integrated circuits; CMOS technology; Carbon nanotubes; Conductivity; Copper; Delay; Electrical resistance measurement; Integrated circuit interconnections; Wires;
Conference_Titel :
Interconnect Technology Conference, 2008. IITC 2008. International
Conference_Location :
Burlingame, CA, USA
Print_ISBN :
978-1-4244-1911-1
Electronic_ISBN :
978-1-4244-1912-8
DOI :
10.1109/IITC.2008.4546976
