A 2.7mW 1MSps 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input ranges

Author

Confalonleri, P. ; Zarnprogno, M. ; Girardi, Francesca ; Nicollini, Germano ; Nagari, Angelo

Author_Institution

Cellular Thermal Div., STMicroelectronics, Agrate Brianza, Italy

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

255

Lastpage

258

Abstract

A CMOS 1 MSps 10 bit charge-redistribution SAR ADC processes single-ended signals with 1 LSB accuracy selectable input ranges up to supply voltage. A new DAC architecture presents the benefits of a differential approach while sampling single-ended signals. Thanks to new low power design solutions in the ADC comparator and the built-in reference buffer, the total ADC power consumption is only 2.7 mW at 2.4 V supply and 1 MSps. The active area is 0.4 mm² in a 0.35 μm CMOS process.

Keywords

CMOS integrated circuits; analogue-digital conversion; buffer circuits; comparators (circuits); low-power electronics; signal sampling; 0.35 micron; 2.4 V; 2.7 mW; CMOS; DAC architecture; analog-to-digital converter; built-in reference buffer; charge-redistribution SAR ADC; comparator; differential single-ended signal sampling; input range accuracy; low power design; programmable input ranges; Analog-digital conversion; CMOS process; Capacitors; Cellular phones; Circuits; Clocks; Energy consumption; Sampling methods; Signal sampling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Print_ISBN

0-7803-8480-6

Type

conf

DOI

10.1109/ESSCIR.2004.1356666

Filename

1356666