A power-efficient 4-PAM signaling scheme with convolutional encoder in space for chip-to-chip communication

Increasing demand for high-speed inter-chip interconnects requires faster links that consume less power. The Shannon limit for the capacity of these links is at least an order of magnitude higher than the data rate of the current state-of-the-art designs. Channel coding can be used to approach the theoretical Shannon limit. Although there are numerous capacity-approaching codes in the literature, the complexity of these codes prohibits their use in high-speed inter-chip applications. A low-complexity signaling scheme is proposed which can achieve 3-5 dB coding gain over uncoded 4-level pulse amplitude modulation (PAM). The receiver for this signaling scheme, along with a regular 4-PAM receiver, was designed and implemented in a 0.18 μm standard digital CMOS technology. Experimental results show that the receiver is functional up to 2.5 Gb/s. The entire receiver for this scheme consumes only 22 mW at 2.5 Gb/s and occupies an area of 0.2 mm².