• DocumentCode
    190618
  • Title

    Accelerating integer-based fully homomorphic encryption using Comba multiplication

  • Author

    Moore, Carl ; O´Neill, Maire ; Hanley, Neil ; O´Sullivan, Elizabeth

  • Author_Institution
    Centre for Secure Inf. Technol., Queen´s Univ. Belfast, Belfast, UK
  • fYear
    2014
  • fDate
    20-22 Oct. 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Fully Homomorphic Encryption (FHE) is a recently developed cryptographic technique which allows computations on encrypted data. There are many interesting applications for this encryption method, especially within cloud computing. However, the computational complexity is such that it is not yet practical for real-time applications. This work proposes optimised hardware architectures of the encryption step of an integer-based FHE scheme with the aim of improving its practicality. A low-area design and a high-speed parallel design are proposed and implemented on a Xilinx Virtex-7 FPGA, targeting the available DSP slices, which offer high-speed multiplication and accumulation. Both use the Comba multiplication scheduling method to manage the large multiplications required with uneven sized multiplicands and to minimise the number of read and write operations to RAM. Results show that speed up factors of 3.6 and 10.4 can be achieved for the encryption step with medium-sized security parameters for the low-area and parallel designs respectively, compared to the benchmark software implementation on an Intel Core2 Duo E8400 platform running at 3 GHz.
  • Keywords
    cloud computing; computational complexity; cryptography; field programmable gate arrays; random-access storage; real-time systems; scheduling; Comba multiplication scheduling method; DSP slices; FHE; Intel Core2 Duo E8400 platform; RAM; Xilinx Virtex-7 FPGA; cloud computing; computational complexity; cryptographic technique; encrypted data; hardware architectures; integer-based fully homomorphic encryption; real-time applications; Clocks; Computer architecture; Digital signal processing; Encryption; Field programmable gate arrays; Hardware;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Systems (SiPS), 2014 IEEE Workshop on
  • Conference_Location
    Belfast
  • Type

    conf

  • DOI
    10.1109/SiPS.2014.6986063
  • Filename
    6986063