Title :
Improved Shallow Trench Isolation For Sub-Halfmicron CMOS
Author :
Cabanal, J.P. ; Haond, M.
Author_Institution :
CNET, Chemin du Vieux Chêne, BP 98, 38243 MEYLAN Cedex, FRANCE
Abstract :
This paper presents new results on shallow trench isolation with the use of tilted field implants for avoiding the field parasitic transistors. Isolation results and gate oxide breakdown voltage are presented and discussed. The fabrication of 0.7 ¿m DLM 16K SRAMs with this type of isolation has been demonstrated with results similar to standard isolation circuits.
Keywords :
CMOS process; Circuits; Design engineering; Etching; MOS devices; MOSFETs; Microelectronic implants; Resists; Standards publication; Transistors;
Conference_Titel :
Solid State Device Research Conference, 1991. ESSDERC '91. 21st European
Conference_Location :
Montreux, Switzerland
