Title :
Sub-Half Micron Isolation Method with Self-Aligned Channel Stopper
Author :
Wakamiya, W. ; Ohno, Y. ; Kimura, S. ; Satoh, S.
Author_Institution :
LSI R&D Laboratory, Mitsubishi Electric Corp., 4-1 Mizuhara, Itami, Hyogo 664, Japan
Abstract :
In this paper, described is a new simple isolation method utilized for realizing sub-half micron devices. Substantially, this isolation method is a dielectric isolation, of which field oxide is the CVD-oxide instead of the thermal oxide with self-aligned chan-stop region.
Keywords :
Anisotropic magnetoresistance; Etching; Fabrication; Impurities; Laboratories; Large scale integration; Leakage current; Microelectronics; Research and development; Resists;
Conference_Titel :
Solid State Device Research Conference, 1991. ESSDERC '91. 21st European
Conference_Location :
Montreux, Switzerland
