A low-power clock generator for system-on-a-chip (SoC) processors

Author

Fahim, Amr M.

Author_Institution

QUALCOMM Inc., San Diego, CA, USA

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

395

Lastpage

398

Abstract

This paper describes a low-power, low-jitter clock generator for system-on-a-chip (SoC) processors. Low-jitter is achieved by using a ROM-less direct digital synthesizer with analog phase interpolation. Low-power is achieved by using differential and feedback replica bias circuit topologies. A 6-bit resolution prototype is implemented in 0.25 μm CMOS technology. Results demonstrate that the clock generator´s area is 0.12 mm² and consumes only 1.5 mA of current consumption at 2.5 V. In comparison with other similar state-of-the-art implementations, this represents savings of 37.5× and 5.87× in area and power consumption, respectively.

Keywords

CMOS integrated circuits; adders; circuit feedback; counting circuits; digital-analogue conversion; direct digital synthesis; interpolation; low-power electronics; system-on-chip; timing jitter; 0.25 micron; 1.5 mA; 2.5 V; 200 MHz; CMOS; MN counter; ROM-less direct digital synthesizer; SoC processors; analog phase interpolation; capacitor based DAC; carry select adder; differential bias circuit; feedback replica bias circuit; low-jitter clock generator; low-power clock generator; system-on-a-chip; CMOS technology; Circuit topology; Clocks; Counting circuits; Energy consumption; Frequency conversion; Interpolation; Jitter; Phase locked loops; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Print_ISBN

0-7803-8480-6

Type

conf

DOI

10.1109/ESSCIR.2004.1356701

Filename

1356701