Floating Gate Structures as Nonvolatile Analog Memory Cells in 1.0μm-LOCOS-CMOS Technology with PZT Dielectrica

In this paper a new floating gate structure of a nonvolatile analog memory cell in 1.0 μm-LOCOS-CMOS-technology is proposed. The new floating gate transistor with Pb(Zr; Ti) O3 as dielectrica between the control and floating gate needs no additional coupling area. After the description of the device fabrication basic characteristics of the ferroelectric material PZT and the new transistor cell are presented. In comparison to measurements on standard floating gate structures it is pointed out that the use of PZT increases or preserves the programming efficiency in spite of a considerable reduction in cell area. In the face of high leakage currents through PZT the memory cells without an additional coupling area can be programmed. For a sufficient support of the tunnel mechanism and for an utilization of the high dielectric constant of Pb(Zr; Ti) O3 a dielectric combination of SiO2 and PZT in analog memory cells seems to be efficient to avoid the occured leakage current.