Title :
Process models and network complexity
Author :
Rietman, Edward A. ; Frye, Robert C. ; Lory, Earl R.
Author_Institution :
AT&T Bell Lab., Murray Hill, NJ, USA
Abstract :
A neural network is used to model a plasma etching system. The network is trained from a large database generated from actual CMOS production runs. One aspect of this model is described which predicts the amount of over-etching into the underlying oxide during silicide gate patterning. Comparing networks of varying complexity, it is found that large, complex networks, which perform better on the task of learning the training data, do not necessarily perform as well on verification. The neural network model is used to extract information regarding the relative influence of various process variables and signatures in the etching process. For such procedures, small, simple networks often prove to be better and more accurate
Keywords :
CMOS integrated circuits; digital simulation; learning (artificial intelligence); neural nets; semiconductor process modelling; sputter etching; CMOS production runs; database; etching process; learning; network complexity; neural network; over-etching; plasma etching system; process variables; signatures; silicide gate patterning; training data; Complex networks; Databases; Etching; Neural networks; Plasma applications; Predictive models; Production; Semiconductor device modeling; Silicides; Training data;
Conference_Titel :
Neural Networks, 1993., IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-0999-5
DOI :
10.1109/ICNN.1993.298739
