Title :
Data routing in dataflow graphs
Author :
De Coster, L. ; Lauwereins, R. ; Peperstraete, J.A.
Author_Institution :
ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
Abstract :
An extension to the cycle-static dataflow graph model is proposed. It is based on the insight that in current digital signal processing (DSP) applications a significant amount of time and resources is spend on the routing of the data between the processing operations. If this part of the application is do be synthesized from a specification to a software or a hardware realization both automatically and efficiently, a systematic approach is to be taken for that data routing. The new model fits in GRAPE, an environment for the fast prototyping DSP systems on arbitrary target architectures, consisting of programmable DSP processors and FPGAs. Besides the definition of the model, the authors present some clarifying examples. They discuss the code generation of data-routing specifications for a specific synthesis path. Finally, a larger example and its implementation validate the model
Keywords :
data flow computing; data flow graphs; digital signal processing chips; field programmable gate arrays; formal specification; signal processing; software prototyping; FPGAs; GRAPE; arbitrary target architecture; code generation; cycle-static dataflow graph model; data routing; data routing specification; digital signal processing applications; fast prototyping environment; hardware realization; processing operations; programmable DSP processors; software realization; specification; synthesis path; Application software; Computer architecture; Digital signal processing; Field programmable gate arrays; Hardware; Pipelines; Prototypes; Routing; Signal synthesis; Software prototyping;
Conference_Titel :
Rapid System Prototyping, 1997. Shortening the Path from Specification to Prototype. Proceedings., 8th IEEE International Workshop on
Conference_Location :
Chapel Hill, NC
Print_ISBN :
0-8186-8064-4
DOI :
10.1109/IWRSP.1997.618851
