• DocumentCode
    1907184
  • Title

    Π-gate nanowires TANOS poly-Si TFT nonvolatile memory

  • Author

    Hung, Min-Feng ; Chen, Jiang-Hung ; Wu, Yung-Chun

  • Author_Institution
    Dept. of Eng. & Syst. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • fYear
    2010
  • fDate
    13-14 June 2010
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    This work we demonstrate a TANOS nonvolatile memory (NVM) with poly-Si nanowire (NW) channels and Pi-gate (II-gate) structure. II-gate structure in this TANOS NVM increase on current (Ion), decrease threshold voltage (Vth) and subthreshold slope (SS), and enlarge the memory window (ΔVth). This NVM device behaves fast program/erase (P/E) speed; 3 V memory window can be achieved by applying 18 V in 10 μs. The 70 % of initial memory window has been maintained after 104 P/E-cycle stress.
  • Keywords
    nanowires; random-access storage; threshold logic; II-gate nanowire; II-gate structure; NVM device; Pi-gate structure; TANOS poly-Si TFT nonvolatile memory; memory window; poly-Si nanowire channel; program/erase speed; subthreshold slope; threshold voltage; time 10 mus; voltage 18 V; voltage 3 V; Logic gates; Nonvolatile memory; Performance evaluation; Programming; Reliability; Scanning electron microscopy; Thin film transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Silicon Nanoelectronics Workshop (SNW), 2010
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-7727-2
  • Electronic_ISBN
    978-1-4244-7726-5
  • Type

    conf

  • DOI
    10.1109/SNW.2010.5562547
  • Filename
    5562547
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1907184