Title :
A physically oriented model to quantify the dynamic noise margin [on-chip noise]
Author :
Gemmeke, T. ; Noll, T.G.
Author_Institution :
EECS, RWTH Aachen University, Germany
Abstract :
The increase in on-chip noise has led to severe signal integrity problems in modern chip design. In a new approach, an analytical, physically motivated model is proposed which quantities the pulse transfer characteristic of a gate, aimed at quick circuit analysis. The accuracy of the model is validated in comparison with simulation results from a circuit simulator. Moreover, its application in a standard design flow is demonstrated. As the model is based on physical circuit parameters, it is also well suited for what-if analysis.
Keywords :
circuit simulation; integrated circuit design; integrated circuit modelling; integrated circuit noise; transient response; analytical noise model; circuit analysis; circuit simulator; design flow; dynamic noise margin; gate pulse transfer characteristic; noise stability; on-chip noise; physically oriented noise model; signal integrity problems; what-if analysis; Capacitance; Chip scale packaging; Circuit noise; Circuit simulation; Noise figure; Noise level; Noise shaping; Pulse circuits; Pulse width modulation inverters; Space vector pulse width modulation;
Conference_Titel :
Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European
Print_ISBN :
0-7803-8480-6
DOI :
10.1109/ESSCIR.2004.1356719
