A low-swing single-ended L1 cache bus technique for sub-90nm technologies

Author

Caputa, P. ; Anders, Mark A. ; Svensson, Christer ; Krishnamurthy, Ram K. ; Borka, Shekhar

Author_Institution

Dept. of Electr. Eng., Linkoping Univ., Sweden

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

475

Lastpage

477

Abstract

This paper describes a 3.3 GHz low-swing single-ended L1 cache bus in 1.2 V, 90 nm dual-Vt CMOS technology. Accurate RLCK-modeling of the interconnect topology has been conducted using a 3D field solver. A signal-swing reduction of 25% and efficient sense amplifier-based receiver are employed to reach 3.3 GHz, 2.24 mW operation at 1.2 V and 110°C. 70% energy and 54% peak-current reduction is achieved over an optimized high-performance conventional dynamic cache bus scheme. The design is fully functional up to 6.1 GHz operating-frequency with a 54% eye opening.

Keywords

CMOS digital integrated circuits; amplifiers; cache storage; flip-flops; integrated circuit interconnections; integrated circuit modelling; system buses; 1.2 V; 110 degC; 2.24 mW; 3.3 GHz; 6.1 GHz; 90 nm; dual-Vt CMOS technology; interconnect RLCK-modeling; low-swing cache bus; on-chip point-to-point interconnect structures; peak-current reduction; sense amplifier based flip-flop receiver; signal-swing reduction; single-ended L1 cache bus; CMOS technology; Circuit topology; Data mining; Delay; Driver circuits; Geometry; Integrated circuit interconnections; Operational amplifiers; Power system interconnection; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Print_ISBN

0-7803-8480-6

Type

conf

DOI

10.1109/ESSCIR.2004.1356721

Filename

1356721