A dual mode channel decoder for 3GPP2 mobile wireless communications

Author

Lin, Chien-Ching ; Shih, Yen-Hsu ; Chang, Hsie-Chia ; Lee, Chen-Yi

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

483

Lastpage

486

Abstract

This paper presents a turbo and Viterbi decoder single chip for 3GPP2 standard. The turbo decoding with a maximum block length of 20,730 and Viterbi decoding with various coding rates are implemented to provide maximum 4.52 Mb/s and 5.26 Mb/s data rates respectively. The memory access is reduced by the input caching scheme. And the system complexity is lowered by the efficient interleaver design. This chip is fabricated in a 0.18 μm six-metal standard CMOS process, and the measured power dissipation is 83 mW while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block.

Keywords

3G mobile communication; CMOS digital integrated circuits; Viterbi decoding; channel coding; interleaved codes; iterative decoding; turbo codes; 0.18 micron; 3GPP2 mobile wireless communications; 4.52 Mbit/s; 5.26 Mbit/s; CMOS; Viterbi decoder; block iterations; coding rate; dual mode channel decoder; input caching; interleaver; memory access reduction; turbo decoder; turbo decoding maximum block length; Bandwidth; Code standards; Concatenated codes; Convolutional codes; Iterative algorithms; Iterative decoding; Power dissipation; Turbo codes; Viterbi algorithm; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Print_ISBN

0-7803-8480-6

Type

conf

DOI

10.1109/ESSCIR.2004.1356724

Filename

1356724