A 2.5 Gbps - 3.125 Gbps multi-core serial-link transceiver in 0.13 μm CMOS

Author

Geurts, Tomas ; Rens, Wim ; Crols, Jan ; Kashiwakura, Shoichiro ; Segawa, Yuichi

Author_Institution

AnSem, Heverlee, Belgium

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

487

Lastpage

490

Abstract

A multi-rate serdes macro that is targeting multi-channel applications has been developed in 0.13 μm. A low-jitter LC VCO PLL can provide the master clock for up to 16 receive and transmit modules. Specific provisions for operation at different data rates are present. The receive module operates at full rate. Comma detection and 8b/10b coding are present. The transmitter has a measured output jitter of 8.1 ps rms at 2.5 Gbps. The receiver has a measured intrinsic jitter tolerance of 0.75 UI. Power consumption for the PLL is 40 mW, a receive and transmit pair consumes 100 mW.

Keywords

CMOS integrated circuits; data communication equipment; phase locked loops; timing jitter; transceivers; voltage-controlled oscillators; 0.13 micron; 100 mW; 2.5 to 3.125 Gbit/s; 40 mW; 8b/10b coding; CMOS; comma detection; jitter tolerance; low-jitter LC VCO PLL; master clock; multichannel serdes; multicore serial-link transceiver; multiple data rates; multirate serdes macro; output jitter; receive modules; transmit modules; CMOS technology; Clocks; Costs; Frequency; Jitter; Phase locked loops; Phase noise; Ring oscillators; Transceivers; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European

Print_ISBN

0-7803-8480-6

Type

conf

DOI

10.1109/ESSCIR.2004.1356725

Filename

1356725