• DocumentCode
    1907706
  • Title

    Drain barrier lowering in HEMTs

  • Author

    Anholt, R.

  • Author_Institution
    Gateway Modeling Inc., Minneapolis, MN, USA
  • fYear
    1998
  • fDate
    1-4 Nov. 1998
  • Firstpage
    99
  • Lastpage
    102
  • Abstract
    Drain barrier lowering gives pinchoff voltages that vary as /spl gamma/Vds, which affects the output conductances. The factor /spl gamma/ depends on the channel aspect ratio X=/spl pi/L/4d, where L is the effective gate length and d is the effective channel depth. For low output conductances we need to minimize /spl gamma/ and maximize the channel aspect ratio X. This paper uses 2D simulations to delineate the effective L and d parameters, and illustrates what can be done to the layer design to minimize d.
  • Keywords
    digital simulation; high electron mobility transistors; semiconductor device models; 2D simulations; DBL effect; HEMTs; PHEMT; channel aspect ratio; drain barrier lowering; output conductance; pinchoff voltages; pseudomorphic HEMT; Analytical models; HEMTs; Helium; Length measurement; MESFETs; MODFETs; MOSFET circuits; PHEMTs; Superlattices; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1998. Technical Digest 1998., 20th Annual
  • Conference_Location
    Atlanta, GA, USA
  • ISSN
    1064-7775
  • Print_ISBN
    0-7803-5049-9
  • Type

    conf

  • DOI
    10.1109/GAAS.1998.722638
  • Filename
    722638