A New Vertically Layered Elevated Hot Carrier Resistant Source/Drain Structure for Deep Submicron MOSFETs

A new vertically layered elevated drain (VLED) structure is proposed, which is suitable, in terms of reliability and performance, for scaling down a MOSFET to the 0.25 ¿m level without reducing the supply voltage below 3.3V. In this structure, a low doped polysilicon spacer is used to defuse the hot carrier problem. The present study of elevated source/drain structures (S/D) exhibiting low doped regions also identifies a new mode of drain current degradation in the linear region due to strong sheet resistance variation along the sidewall oxide interface.