Title :
OPAM: an efficient output phase assignment for multilevel logic minimization
Author :
Wey, Chin-Long ; Chang, Sin-Min ; Jou, Jing-Yang
Author_Institution :
Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Abstract :
When a multiple-output function (z1, z2, . . ., zm) of multilevel logic is realized by complex gates, the option often exists to realize either zi or its complement for each output. An efficient output phase assignment for the multilevel logic minimization (OPAM) is presented. The results of this study show that the proposed algorithm further reduces the literal count of the optimized network obtained by MIS (a multilevel logic minimization system)
Keywords :
logic CAD; minimisation; OPAM; complex gates; literal count reduction; multilevel logic minimization; multiple-output function; output phase assignment; Automatic logic units; CMOS logic circuits; Equations; Inverters; Logic design; Minimization methods; Programmable logic arrays; Timing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63369
