Assertion-based verification of signal processing systems with affine arithmetic

This paper describes a novel method to verify typical properties of systems with parameter deviations. These parameter deviations have an impact on a system behavior causing it to deviate from its ideal behavior. The concept of Affine Arithmetic is used to model typical errors and uncertainties in today´s analog-mixed signal systems. The method which is proposed is a combination of assertions and Affine Arithmetic where Affine Arithmetic is also used to model typical properties of signal processing specifications. The target of the proposed method is to speed up the detection of errors in system behavior, which cause the violation of system properties. The applicability of the proposed method is demonstrated through two small examples.