MOSFET scalability limits and "new frontier" devices

Author

Antoniadis, D.A.

Author_Institution

Microsystems Technol. Lab., MIT, Cambridge, MA, USA

fYear

2002

fDate

11-13 June 2002

Firstpage

2

Lastpage

5

Abstract

Silicon-based MOSFETs are scalable to gate-lengths around 10 nm but will fall well short of commensurate performance enhancement. High mobility materials and device structures that eliminate the use of doping for electrostatic control will have to be incorporated in future CMOS technologies, along with very low contact resistance processes. New frontier FETs incorporating entirely new transport principles show promise but are still far from practical implementation.

Keywords

CMOS integrated circuits; MOSFET; carrier mobility; contact resistance; integrated circuit design; integrated circuit technology; semiconductor technology; technological forecasting; 10 nm; CMOS technologies; FET transport principles; MOSFET scalability limits; SiO/sub 2/-Si; device structures; doping-based electrostatic control elimination; gate-lengths; high mobility materials; low contact resistance processes; performance enhancement; practical implementation; silicon-based MOSFET; CMOS process; CMOS technology; Doping; Electrostatics; FETs; Lithography; MOSFET circuits; Scalability; Silicon; Telephony;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7312-X

Type

conf

DOI

10.1109/VLSIT.2002.1015365

Filename

1015365