Instruction set architecture of an efficient pipelined dataflow architecture

A highly pipelined static dataflow architecture based on an argument-fetching data-driven principle has recently been proposed. It separates the data-driven instruction scheduling mechanism from the actual instruction execution unit, avoiding the unnecessary overhead of data token movement that exists in other proposals of dataflow architectures. Work carried out on the instruction set design and machine program format is described. The implementation of long-latency operations-the structure memory operations and interprocessor communication operations-is discussed, as is the implementation of FIFO (first-in-first-out) buffers. The design of an assembler and instruction-set interpreter is outlined