DocumentCode
1907951
Title
Optimisation of silicon fed fabrication for space application
Author
Wang, L. ; Stevens, R. ; Huq, S.E. ; Loader, I. ; Kent, B.J. ; Aplin, K.L. ; She, J.C.
Author_Institution
Central Microstructure Facility, Rutherford Appleton Lab., Didcot, UK
fYear
2003
fDate
7-11 July 2003
Firstpage
83
Lastpage
84
Abstract
This paper focuses on the design issues and process calibrations of the fabrication of a silicon field emission device on N type 100-mm diameter silicon wafer.
Keywords
electron field emission; elemental semiconductors; field emitter arrays; silicon; sputtered coatings; 100 mm; AlN; Si; design issues; process calibration; silicon FED fabrication; silicon field emission device; silicon wafer; space application; Dry etching; Fabrication; Laboratories; Rough surfaces; Silicon; Space technology; Surface roughness; Testing; Voltage; Wet etching;
fLanguage
English
Publisher
ieee
Conference_Titel
Vacuum Microelectronics Conference, 2003. Technical Digest of the 16th International
Conference_Location
Osaka, Japan
Print_ISBN
4-8181-9515-4
Type
conf
DOI
10.1109/IVMC.2003.1222994
Filename
1222994
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