Title :
Parasitic breakdown control in HVIC process integration
Author :
Murray, A.F.J. ; Lane, W.A. ; Cahill, G.G. ; Barrett, J.D.
Author_Institution :
Institute of Advanced Microelectronics, National Microelectronics Research Centre, University College, Lee Maltings, Prospect Row, Cork, Ireland.
Abstract :
This paper presents an investigation of two problems crucial to parasitic control in HVIC´s. The first is a spacing problem, where the breakdown of an n-well is shown to be critically dependent on the spacing to the field-implant. The second is a wiring problem, where a grounded polysilicon field plate is used to prevent inversion of the silicon surface under a 200-V wire.
Keywords :
Breakdown voltage; Circuits; Electric breakdown; Implants; Low voltage; Microelectronics; Process control; Silicon; Voltage control; Wiring;
Conference_Titel :
Solid State Device Research Conference, 1991. ESSDERC '91. 21st European
Conference_Location :
Montreux, Switzerland
