DocumentCode
1908059
Title
Fully Scalable Gain Memory Cell for Future Drams
Author
Krautschneider, W.H. ; Risch, L. ; Lau, K. ; Schmitt-Landsiedel, D.
Author_Institution
Siemens Comp. Inc., 1000 River St., Essex Junction, VT 05452, USA
fYear
1991
fDate
16-19 Sept. 1991
Firstpage
367
Lastpage
370
Abstract
A dynamic memory cell is described in which charge is stored on the gate capacitance of a MOS transistor rather than on a discrete capacitor. This transistor is used as an amplifying device, so that the output charge is much greater than the charge stored in the cell. The memory cell can be scaled down without performance loss.
Keywords
Capacitance; DRAM chips; MOS capacitors; MOSFETs; Microelectronics; Performance loss; Random access memory; Research and development; Rivers; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1991. ESSDERC '91. 21st European
Conference_Location
Montreux, Switzerland
Print_ISBN
0444890661
Type
conf
Filename
5435307
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