Title :
TLM POWER3: Power estimation methodology for SystemC TLM 2.0
Author :
Greaves, David ; Yasin, Mehboob
Author_Institution :
Comput. Lab., Univ. of Cambridge, Cambridge, UK
Abstract :
We report on a SystemC add-on library which extends every SystemC module with non-functional data regarding power consumption and physical layout and which accumulates and estimates dynamic energy usage. It supports both phase/mode power modelling and energy-per-transaction logging for TLM (transactional-level modelling). Wiring energy is computed by counting bit-level activity within the TLM generic payload. Each leaf component can also register its physical dimensions to facilitate a wire length estimator that traverses the SystemC model hierarchy using either full placement or Rent´s rule estimators. It also supports dynamic voltage islands and inter-chip wiring, where each transaction can consume energy according to the current supply voltage of the relevant islands and the nature of the interconnect. We report on basic peformance from some SPLASH-2 benchmarks running on a modelled OpenRISC quad-core platform.
Keywords :
DRAM chips; electronic design automation; interconnections; power supplies to apparatus; reduced instruction set computing; wires (electric); OpenRISC quadcore platform; Rent rule estimators; SPLASH-2 benchmarks; SystemC TLM 2.0; SystemC add-on library; SystemC model hierarchy; SystemC module; TLM POWER3; TLM generic payload; bit-level activity; dynamic energy usage estimation; dynamic voltage islands; energy-per-transaction logging; interchip wiring energy; interconnect nature; leaf component; mode power modelling; nonfunctional data; physical layout; power consumption; power estimation methodology; transactional-level modelling; Computational modeling; Libraries; Payloads; Power demand; Random access memory; Time domain analysis; Time varying systems;
Conference_Titel :
Specification and Design Languages (FDL), 2012 Forum on
Conference_Location :
Vienna
Print_ISBN :
978-1-4673-1240-0