Title :
Low standby power CMOS with HfO/sub 2/ gate oxide for 100-nm generation
Author :
Pidin, S. ; Morisaki, Y. ; Sugita, Y. ; Aoyama, T. ; Irino, K. ; Nakamura, T. ; Sugii, T.
Author_Institution :
Fujitsu Labs. Ltd., Tokyo, Japan
Abstract :
We have fabricated 55-nm poly-Si gated n- and p-MOSFETs with HfO/sub 2/ gate dielectric of 3-nm physical thickness deposited by atomic layer deposition (ALD). A conventional CMOS process was used with high-temperature S/D anneal of /spl ges/1000/spl deg/C, cobalt-silicide and pocket implants. The devices showed very promising characteristics for low standby power applications due to drastic reduction of gate leakage current.
Keywords :
CMOS integrated circuits; annealing; atomic layer epitaxial growth; dielectric thin films; doping profiles; hafnium compounds; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; ion implantation; leakage currents; low-power electronics; nanotechnology; permittivity; 100 nm; 1000 C; 3 nm; 55 nm; ALD; CMOS; CoSi/sub 2/; HfO/sub 2/ gate oxide; HfO/sub 2/-Si; atomic layer deposition; cobalt-silicide; gate dielectric; gate leakage current; high-temperature S/D anneal; low standby power CMOS; pocket implant; poly-Si gated n-MOSFET; poly-Si gated p-MOSFET; Annealing; CMOS technology; Dielectrics; Hafnium oxide; Implants; Leakage current; MOSFET circuits; Power generation; Standby generators; Threshold voltage;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015375
