DocumentCode
1908340
Title
20 Gbit/s 2:1 Multiplexer Using 0.3 μm Gate Length Double Pulse Doped Quantum Well GaAs/AlGaAs Transistors
Author
Nowotny, U. ; Lang, M. ; Berroth, M. ; Hurm, V. ; Hülsmann, A. ; Kaufel, G. ; Köhler, K. ; Raynor, B. ; Schneider, Jo.
Author_Institution
Fraunhofer Institut f?r Angewandte Festk?rperphysik, Tullastr. 72, D-7800 Freiburg, Germany
fYear
1991
fDate
16-19 Sept. 1991
Firstpage
323
Lastpage
326
Abstract
A high speed 2:1 multiplexer circuit in source coupled FET logic has been developed and fabricated using a recessed gate process for enhancement and depletion transistors with 0.3μm gate length. First results show a data rate of over 20 Gbit/s at 5 V supply voltage and 250 mW power consumption. The output voltage swing is adjustable between 0.3 V and 0.8 V for a 50 Ohm load. The out-put level can be varied between +1 V an -1 V. Comparison between simulation and measurement shows very good agreement.
Keywords
Circuit simulation; Circuit testing; Energy consumption; Gallium arsenide; Logic testing; Multiplexing; SPICE; Switches; Test equipment; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1991. ESSDERC '91. 21st European
Conference_Location
Montreux, Switzerland
Print_ISBN
0444890661
Type
conf
Filename
5435318
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