Suppression of leakage current in SOI CMOS LSIs by using silicon-sidewall body-contact (SSBC) technology

Author

Kotani, N. ; Ito, S. ; Yasui, T. ; Wada, Atsushi ; Yamaoka, T. ; Hori, T.

Author_Institution

ULSI Process Technol. Dev. Center, Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan

fYear

2002

fDate

11-13 June 2002

Firstpage

44

Lastpage

45

Abstract

This paper clarifies two SOI-specific leakage components, STI-induced punchthrough and gate-oxide leakage, found especially in large-scale integration, and proposes a new SOI technology: silicon-sidewall body-contact (SSBC). Without layout penalty and process complexity, SSBC realizes self-aligned body contact to the substrate, which suppresses gate-oxide leakage, and prevents the SOI body from being mechanically stressed, thus eliminating punchthrough leakage. SSBC is promising for scaled SOI CMOS LSIs.

Keywords

CMOS integrated circuits; dielectric thin films; electrical contacts; isolation technology; large scale integration; leakage currents; silicon-on-insulator; SOI CMOS LSI; SOI body mechanical stress prevention; SOI technology; SOI-specific leakage components; SSBC technology; STI-induced punchthrough leakage; Si-SiO/sub 2/; gate-oxide leakage; large-scale integration; leakage current suppression; process complexity; self-aligned body contact; silicon-sidewall body-contact technology; Breakdown voltage; CMOS process; CMOS technology; Degradation; Etching; Large scale integration; Leakage current; Oxidation; Silicon compounds; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7312-X

Type

conf

DOI

10.1109/VLSIT.2002.1015381

Filename

1015381