Title :
High soft-error tolerance body-tied SOI technology with partial trench isolation (PTI) for next generation devices
Author :
Hirano, Y. ; Iwamatsu, T. ; Shiga, K. ; Nii, K. ; Sonoda, K. ; Matsumoto, T. ; Maeda, S. ; Yamaguchi, Y. ; Ipposhi, T. ; Maegawa, S. ; Inoue, Y.
Author_Institution :
ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
It was proven that the body-tied SOI technology with partial trench isolation (PTI) has significant high soft-error immunity. As compared with the bulk, a three-order reduction of the soft-error rate for a 0.18 /spl mu/m SOI 4 Mbit SRAM with the PTI was successfully realized by the balanced combination of the SOI thickness and well resistance. It is estimated that the soft-error immunity for the floating-body device degrades because large charge collection is induced by not only the body strike but also the drain strike. A design guideline of the SOI structure to suppress soft errors is presented. According to the guideline, beyond 0.13 /spl mu/m node, high soft-error immunity for the body-tied SOI device was projected as compared with the bulk as well as the body-floating SOI device.
Keywords :
CMOS memory circuits; SRAM chips; error handling; isolation technology; semiconductor device measurement; silicon-on-insulator; 0.13 micron; 0.18 micron; 4 Mbit; CMOS technology; PTI; SOI SRAM; SOI structure design guideline; SOI thickness; Si-SiO/sub 2/; body strike; body-floating SOI device; body-tied SOI device; body-tied SOI technology; charge collection; drain strike; floating-body device; partial trench isolation; soft-error immunity; soft-error rate; soft-error tolerance; well resistance; Alpha particles; Current measurement; Electrons; Isolation technology; MOSFET circuits; Neutron spin echo; Paper technology; Random access memory; Testing; Voltage;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015383
