FPGA Implementation of High Speed VLSI Architectures for AES Algorithm

In this paper, we have proposed high data throughput AES hardware architecture by partitioning ten rounds into sub-blocks of repeated AES modules. The blocks are separated by intermediate buffers providing a complete ten stages of AES pipeline structure. In addition, the AES is internally evenly divided to ten pipeline stages, with the additional feature that the shift rows block (Shift Row) is structured to operate before the byte substitute (Byte Substitute) block. This proposed swapping operation has no effect on the AES encryption algorithm, however, it streamlines the processing of four blocks of data in parallel rather than 16 blocks, which is considered as the key advantage for area saving. We have evaluated the performance of our implementation in terms of throughput rate and hardware area for Xilinx´s SPARTAN-3 FPGA. The simulation results show that the proposed AES has higher throughput rate of about 4.25% than the general AES pipeline structure with a saving hardware area of 56%.