A Four Quadrants Parallel-Recursive 2-D DCT/IDCT VLSI Architecture

A 2D DCT/IDCT is widely used in image compression system. However, due to its computational intensity, dedicated hardware architecture is required to compress large video data in real-time. This paper propose an efficient architecture to concurrently process all macro block data in 2D DCT/IDCT. As a result, the processing speed is increased up to 13.30 times and no transposition buffer is required. Eliminating transposition buffer is significantly reduced the design size and the processing latency. Moreover, proposed architecture critical path consists only three stage adder which improve system speed. The proposed architecture also does not require a large bit width to produce high quality reconstructed image (High PSNR). It is because the architecture use the multiplier just once for each data. Therefore, the rounding of intermediate data does not cumulative. The design has been implemented and verified in FPGA to real-time show compression and decompression of a moving JPEG. The design has been also synthesized using CMOS 0.18μm technology library that results in 12.37 ns critical path.