Energy recovery clock gating scheme and negative edge triggering flip-flop for low power applications

Energy recovery is a technique developed for low power digital circuits. Energy recovery clocking is an effective method for reducing the clock power in which the conventional square wave clock signal is replaced by a trapezoidal clock. This modification in the clock signal prevents the application of existing clock gating solutions. In this paper, a clock gating solution for energy recovery clocking is proposed by gating the flip-flops. Further, all the existing energy recovery clocked flip-flops are positive edge triggered. But in a synchronous system, it is advantageous to have both positive and negative edge triggered flip-flops in the same system. There has not been a negative edge triggered energy recovery flip-flop in the literature so far. In this paper, we propose a design of negative edge triggered flip-flop with the clock gating feature. The proposed design is simulated using the industrial standard Austria micro systems 350nm process technology Tanner spice(T-spice) tool. The simulation results show that the design is as power efficient as the existing positive edge triggered energy recovery flip-flops and is well suited for low power applications.